1. Field of the Invention
This invention relates generally to a computer graphics/video display system, and more specifically to an multi-function controller in a computer graphics/video display system.
2. Description of the Related Art
FIG. 1 illustrates a conventional computer graphics/video display system 10 that generates a graphics or video image. This system includes three buses: a host bus 22, a Peripheral Component Interconnect/Interface (PCI) bus 24 and an Industry Standard Architecture (ISA) bus 26. The host bus 22 can run at 50-100 MHz and can be 8 or more bytes wide. The PCI bus 24, which is an industry standard bus, runs at 33 MHz and is 4 bytes wide, and the ISA bus 26, which is also an industry standard bus, runs at 6-8 MHz and is two bytes wide.
A central processing unit (CPU) 28 and a cache memory 30 are connected to the host bus 22. A cache controller/system memory controller/PCI bridge unit 32, connected to both the host bus 22 and the PCI bus 24, controls the cache 30 and a system memory device 34 and controls information flow between the host bus 22 and the PCI bus 24. A data buffer 36, connected to both the host bus 22 and the PCI bus 24, stores data traveling to and from the memory device 34. A PCI bus master 35 controls the transfer of information on the PCI bus 24 to and from the system memory 34.
A south bridge 42, which is connected between the ISA bus 26 and the PCI bus 24, controls information traveling between the PCI bus 24 and the ISA bus 26. An ISA bus master 44 controls the flow of information on the ISA bus 26 to and from the system memory 34. In response to a command from the CPU 28, a graphics processor 46 generates graphics data, which is then stored in a local frame buffer 47 or displayed as an image on a monitor 20. In response to a command from the CPU 28, a video processor 37 generates video data for display on monitor 20.
A disadvantage with the system illustrated in FIG. 1 is that the PCI bus 24, to which the graphics and video processors are connected, does not have enough speed to allow the graphics and video processors to perform the functions required by many advanced graphics/video display systems. Specifically, the graphics and video processors cannot access system memory 34 as quickly as is desired. Additionally, the system illustrated in FIG. 1 does not give the graphics and video processors direct access to system memory 34, thus resulting in a higher cost because a local frame buffer 47 must be used. Therefore, there is a need for a graphics/video display system which will have a graphics/video processor that can easily access system memory, which will have the capacity to perform functions required by advanced graphics systems, and which will be economical.
The present invention provides a method and a system for displaying graphics or video images on a monitor. Using a novel architecture, the present invention combines the above-described functions of the graphics processor, the video processor, and the system memory controller/cache controller/PCI bridge unit into an multi-function controller connected to both the host bus and the PCI bus (or other similar buses). The multi-function controller may comprise one or more chips.
By incorporating the graphics/video processor into a controller that is linked to the host bus, the present invention overcomes the conventional system limitations associated with coupling the graphics processor to the PCI bus. Since the host bus is faster than the PCI bus, information can travel faster to and from the graphics/video processor than it would travel if the graphics/video system were just coupled to the PCI bus.
Moreover, in one embodiment, the graphics frame buffer and the system memory are combined into a unified system memory, which is controlled by the multi-function controller. A unified system memory has more space than a regular frame buffer, and using the unified system memory uses less parts than using both a frame buffer and a separate system memory. Additionally, having the multi-function controller control the unified system memory allows the graphics/video processor to have direct access to the unified system memory.
In a preferred embodiment, the multi-function controller is divided into a combined PCI bridge/cache controller and a unified graphics/video controller. The combined PCI bridge/cache controller includes a PCI bridge and a cache controller. The unified graphics/video controller includes a graphics/video processor and a system memory controller. By integrating the PCI bridge and cache controller and by integrating the graphics/video processor and the system memory controller, the number of chips in the system of the present invention is reduced.
The combined PCI bridge/cache controller and the unified graphics/video processor are coupled by a communications link. All commands for the unified graphics/video controller from various components in the system of the present invention are sent to the combined PCI bridge/cache controller, which via the communications link, passes the commands to the unified graphics/video controller. Sending all commands for the unified graphics/video controller to the combined PCI bridge/cache controller promotes efficiency because commands are then directly sent to the unified graphics/video controller from only one place.